The present invention generally relates to a method for fabricating a thin film transistor (TFT) and device formed by such method and more particularly, relates to a method for fabricating a TFT that has high aperture ratio and low contact resistance by depositing a source/drain metal layer directly on a n+ amorphous silicon layer and a transparent electrode layer on top of the TFT structure and device formed by such method.
In recent years, large liquid crystal cells have been used in flat panel displays. The liquid crystal cells are normally constructed by two glass plates joined together with a layer of a liquid crystal material sandwiched inbetween. The glass substrates have conductive films coated thereon with at least one of the substrates being transparent. The substrates are connected to a source of power to change the orientation of the liquid crystal material. A possible source of power is a thin film transistor that is used to separately address areas of the liquid crystal cells at very fast rates. The TFT driven liquid crystal cells can be advantageously used in active matrix displays such as for television and computer monitors.
As the requirements for resolution of liquid crystal monitors increase, it becomes desirable to address a large number of separate areas of a liquid crystal cell, called pixels. For instance, in a modem display panel, more than 3,000,000 pixels may be present. At least the same number of transistors must therefore be formed on the glass plates so that each pixel can be separately addressed and left in the switched state while other pixels are addressed.
Thin film transistors are frequently made with either a polysilicon material or an amorphous silicon material. For TFT structures that are made of amorphous silicon material, a common structure is the inverted staggered type which can be back channel etched or tri-layered. The performance of a TFT and its manufacturing yield or throughput depend on the structure of the transistor. For instance, the inverted staggered back channel etched TPT can be fabricated with a number of six masks, whereas other types of inverted staggered TFT require a minimum number of nine masks. The specification for a typical inverted staggered back channel etched TFT includes an amorphous silicon that has a thickness of 3,000 xc3x85, a gate insulator of silicon nitride or silicon oxide, a gate line of Mo/Ta, a signal line of Al/Mo and a storage capacitor. The requirement of a thick amorphous silicon layer in the TFT device is a drawback for achieving a high yield fabrication process since deposition of amorphous silicon is a slow process. A major benefit for the amorphous silicon TFT is its low leakage current which enables a pixel to maintain its voltage. On the other hand, an amorphous silicon TFT has the drawback of a low charge current (or on current) which requires an excessive amount of time for a pixel to be charged to its required voltage.
A second type of TFT is made by using a polysilicon material. Polysilicon is more frequently used for displays that are designed in a smaller size, for instance, up to three inch diagonal for a projection device. At such a small size, it is economical to fabricate the display device on a quartz substrate. Unfortunately, large area display devices cannot be normally made on quartz substrates. The desirable high performance of polysilicon can therefore be realized only if a low temperature process can be developed to enable the use of non-quartz substrates. For instance, in a more recently developed process, large area polysilicon TFT can be manufactured at processing temperatures of less than 600xc2x0 C. In the process, self-aligned transistors are made by depositing polysilicon and gate oxide followed by source/drain regions which are self-aligned to the gate electrode. The device is then completed with a thick oxide layer, an ITO layer and aluminum contacts.
Polysilicon TFTs have the advantage of a high charge current (or current) and the drawback of a high leakage current. It is difficult to maintain the voltage in a pixel until the next charge in a polysilicon TFT due to its high leakage current. Polysilicon also allows the formation of CMOS devices, which cannot be formed by amorphous silicon. For the fabrication of larger displays, a higher mobility may be achieved by reducing the trap density around the grain boundaries in a hydrogenation process.
FIG. 1 shows an enlarged, cross-sectional view of a conventional amorphous silicon TFT structure. Amorphous TFT 10 is built on a low cost glass substrate 12. On top of the glass substrate 12, a gate electrode 14 is first deposited of a refractory metal such as Cr, Ar or Al alloy and then formed. A gate insulating layer 16 is normally formed in an oxidation process. For instance, a high density TaOx on a Ta gate can be formed to reduce defects such as pin holes and to improve yield. Another gate insulating layer 20 is then deposited of either silicon oxide or silicon nitride. An intrinsic amorphous silicon layer 22 is then deposited with a n+ doped amorphous silicon layer 24 deposited on top to improve its conductivity. Prior to the deposition of the doped amorphous silicon layer 24, an etch stop 26 is first deposited and formed to avoid damages to the amorphous silicon layer 22 in a subsequent etch process for a contact hole. The doped amorphous silicon layer 24 is formed by first depositing the amorphous silicon layer in a chemical vapor deposition process and then implanting ions in an ion implantation process. Boron ions are normally used to achieve n+ polarity. A drain region 30 and a source region 32 are then deposited and formed with a pixel electrode layer 34 of ITO (indium-tin-oxide) material deposited and formed on top. The drain region 30 and the source region 32 are normally deposited of a conductive metal layer. A suitable conductive metal may be a bilayer of Cr/Al. The structure is then passivated with a passivation layer 36.
A second conventional inverted staggered type TFT 40 is shown in FIG. 2. The TFT 40 is frequently called the back channel etched type inverted staggered TFT. A gate electrode 42 is first formed on a non-conducting glass substrate 38. The gate electrode 42 is connected to a gate line (not shown) laid out in the row direction. A dielectric material layer 44 of either silicon oxide or silicon nitride is used to insulate the gate electrode 42. After an amorphous silicon layer 46 and a contact layer 48 are sequentially deposited, patterned and etched, source electrode 50 and drain electrode 52 are formed to provide a channel 54 in-between the two electrodes, hence the name back channel etched TFT. The source electrode 50 of each TFT is connected to a transparent pixel electrode 56 independently formed in the area surrounded by the gate lines and the drain lines (not shown). A transparent passivation layer 58 of a material such as silicon nitride is deposited on the completed structure.
As shown in FIG. 2, the gate electrode 42 is frequently formed of chromium or other similar metals on the transparent glass substrate 38. The dielectric layer 44 of gate oxide or silicon nitride is formed to insulate the upper surface of the glass substrate 38 including the top surface of the gate electrode 42. A semi-conducting layer 46, which may be formed of amorphous silicon is stacked on the dielectric film 44 over the gate electrode 42. The drain electrode 52 and the source electrode 50 are formed on the semi-conducting film 46 and are separated from each other by a predetermined distance forming the channel section 54. The two electrodes each has a contact layer of 48 and a metal layer which are electrically connected to the semi-conducting layer 46. The transparent electrode 44 may be formed of ITO.
In modern TFT devices utilized for driving LCD, it is desirable to have a high aperture ratio and a low contact resistance in the TFT. The aperture ratio of a TFT is defined as the ratio of the transparent area on the black matrix to the unit cell area. The larger the aperture ratio of a TFT, the better the performance due to a higher light intensity obtained. A low contact resistance in a TFT is desirable since that the performance of the transistor can be improved by reducing the driving current. In conventional TFT-LCD devices which require at least 6 masks for its fabrication, it is not possible to obtain the benefits of both a high aperture ratio and a low contact resistance between source/drain metal layer and n+ amorphous silicon (or a-Si) layer. Furthermore, a conventional 6-mask TFT process for making high aperture ratio TFT""s does not produce storage capacitors on the device which have satisfactory performance stability.
It is therefore an object of the present invention to provide a high aperture ratio and low contact resistance thin film transistor structure that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for fabricating a high aperture ratio and low contact resistance TFT structure by depositing directly a source/drain metal layer on a n+ a-Si layer for achieving low contact resistance.
It is a further object of the present invention to provide a method for fabricating a high aperture ratio and low contact resistance TFT structure by depositing a transparent electrode layer on top of the TFT structure and into contact openings such that the high aperture ratio characteristic can be realized.
It is another further object of the present invention to provide a method for fabricating a high aperture ratio and low contact resistance TFT structure by pre-etching a gate nitride layer to at least 20% of its original thickness during an amorphous silicon island formation process by dry etching.
It is still another object of the present invention to provide a method for fabricating a high aperture ratio and low contact resistance TFT structure by directly depositing a source/drain metal layer on a n+ a-Si layer before the patterning of the silicon layer.
It is yet another object of the present invention to provide a method for fabricating a high aperture ratio and low contact resistance TFT structure by depositing an organic polymeric layer on top of the TFT structure for passivation prior to a transparent electrode layer.
It is still another further object of the present invention to provide a high aperture ratio and low contact resistance TFT structure which includes a polymeric passivation layer overlying the structure and a transparent electrode layer on top of the polymeric passivation layer for achieving high aperture ratio of the structure.
In accordance with the present invention, a method for fabricating a high aperture ratio and low contact resistance TFT structure and device formed by such method are disclosed.
In a preferred embodiment, a method for fabricating a high aperture ratio TFT structure can be carried out by the operating steps of first providing a glass substrate, then forming metal gate on the substrate, then depositing gate nitride, intrinsic amorphous silicon and n+ amorphous silicon layers sequentially on the substrate embedding the metal gate, then depositing a source/drain metal layer on the n+ amorphous silicon layer, then patterning and etching the source/drain metal layer to expose the n+ amorphous silicon layer in an opening for a back channel, then defining an amorphous silicon island by a dry etching method and over-etching the gate nitride layer by at least 20% of its original thickness, then etching the back channel to expose the intrinsic amorphous silicon layer, then depositing a passivation nitride layer on top of the TFT structure, etching away the passivation nitride layer in the back channel and in a contact opening to a substrate by a first etch recipe, etching away the intrinsic amorphous silicon layer in the back channel by a second etch recipe, then depositing an organic polymer layer on top of the TFT structure and forming a contact opening to the source/drain metal layer, and depositing a transparent electrode layer on top of the TFT structure and into the contact opening with the organic polymer layer insulating the transparent electrode from other conductive layers.
The method for fabricating a high aperture ratio TFT structure may further include the step of forming the metal gate from a material selected from the group consisting of Al, Cr, W, Mo, Ta and their alloys. The method may further include the step of forming the metal gate in a bi-layer structure, and the step of forming the source/drain metal layer sandwiched between two buffer metal layers. The two buffer metal layers may be selected from the group consisting of Cr, Mo and Ti. The method may further include the step of depositing the source/drain metal layer of aluminum or an aluminum alloy, or the step of defining the amorphous silicon island by a dry etching method utilizing an etchant mixture of SF6, Cl2 and O2.
The dry etching method for defining the amorphous silicon island preferably over-etches the gate nitride layer by at least 50% of its original thickness. The method may further include the step of etching away the passivation nitride layer in the back channel and in a contact opening to the glass substrate by a first etch recipe that has an etch rate ratio of SiNx:a-Si of not less than 5, or the step of etching away the intrinsic amorphous silicon layer in the back channel by a second etch recipe that has an etch rate ratio of a-Si:SiNx of not less than 5. The transparent electrode layer may be formed of indium-tin-oxide.
In an alternate embodiment, a method for making a low contact resistance TFT structure may be carried out by the steps of first providing a substantially transparent glass substrate, then forming a metal gate on the substrate from a first metal layer, then depositing gate nitride, intrinsic amorphous silicon and n+ amorphous silicon layers sequentially on the substrate embedding the metal gate, then depositing a second metal layer on the n+ amorphous silicon layer for forming source/drain electrodes that have low contact resistance, then patterning and etching the second metal layer to expose the n+ amorphous silicon layer in an opening for a back channel, then defining an amorphous silicon island by a dry etching method and simultaneously pre-etching the gate nitride layer, then etching the back channel to expose the intrinsic amorphous silicon layer, depositing a passivation nitride layer on top of the TFT structure, etching away the passivation nitride layer and the intrinsic amorphous silicon layer in the back channel by a two-step dry etching process, then depositing a polymeric dielectric layer on top of the TFT structure and forming a contact opening to the source/drain metal layer, and then depositing a transparent electrode layer on top of the TFT structure and into the contact opening.
The method may further include the step of forming the metal gate from a material of Al, Cr, W, Mo, Ta or their alloys, the method may further include the step of forming the metal gate in a bi-layer structure. The method may further include the step of forming the second metal layer sandwiched between two buffer metal layers which may be selected from the group consisting of Cr, Mo and Ti. The method may further include the step of depositing the second metal layer of aluminum or of an aluminum alloy.
The method may also include the step of defining the amorphous silicon island by a dry etching method utilizing an etchant mixture of SF6, Cl2 and O2. The dry etching method for defining the amorphous silicon island pre-etches the gate nitride layer by at least 20% of its original thickness. The method may further include the step of etching away the passivation nitride layer and the intrinsic amorphous silicon layer in the back channel opening by a first etch recipe which has an etch rate ratio of SiNx:a-Si of not less than 5, followed by a second etch recipe which has an etch rate ratio of a-Si:SiNx of not less than 5.
The present invention is further directed to a high aperture ratio and low contact resistance TFT structure which includes a glass substrate, a metal gate on the substrate, a gate nitride layer embedding the metal gate, an intrinsic amorphous layer overlying the gate nitride layer, a passivation nitride layer deposited in a contact opening formed in a n+ amorphous silicon layer and a source/drain metal layer while on top of and in contact with the intrinsic amorphous silicon layer, a polymeric passivation layer overlying the passivation nitride layer and filling the contact opening, and a transparent electrode layer on top of the TFT structure providing electrical communication with the source/drain metal layer and functions as a top electrode in contact with the gate nitride layer forming a capacitor with the metal gate as a lower electrode.
The device may further include a source/drain metal layer which intimately joins the n+ amorphous silicon layer for contributing to a low contact resistance for the TFT structure. The transparent electrode layer may be formed of indium-tin-oxide. The metal gate may be formed of a material selected from the group consisting of Al, Cr, W, Mo, Ta and their alloys. The capacitor may be formed by the transparent electrode layer, the gate nitride layer and the metal gate providing improved storage capacitance.